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Honored Contributor
Honored ContributorNeed Help to Verify Timing Constraints On Output Pins to External Device
Hi, I'm relatively new in FPGA designing, so forgive me if my question seem simple. The project I am working on involves using a Cyclone V to control 4 external DDS chips (AD9915). So I'...
Altera_ForumHonored Contributor
Honored ContributorOpen the PLL in the Megawizard or QSYS and look at the compensation mode. If it's direct, than it's not compensating, but Normal mode means it has a clock fedback into the PLL which is used to shift the output clock, i.e. it tries to align the clock at the end of the global clock tree with the time it enters the PLL. Basically it's like a negative shift of a few ns.
