Need Help to Verify Timing Constraints On Output Pins to External Device

wzs, I can't really read the screenshot with your timing analysis, but yes, 6.3ns is long for a clock. I would expect the physical layout to be: dedicated_clk_input -> PLL -> Global -> output register -> output. The input to register could be ~4-5ns, but that's all the components and without the PLL in any compensation mode. So make sure the PLL is compensating. If there is no PLL, that may be your problem.

I think it should meet timing then, but not with a lot of margin. If your board is like your last post, where a clock drives both the FPGA and the external device, then what you're doing is correct(although the output delay max should be 2.0, as that's the setup timing I believe). If the external device sends out a clock and you're getting data back, it's unlikely that full roundtrip delay can occur in one cycle.