Need Help to Verify Timing Constraints On Output Pins to External Device

I think some details were given by Rysc. Let me recap my view:

If your interface was source synchronous then it should have gone well certainly for the one register case.

In your case your interface is not source synchronous. It is system synchronous (same clock to both chips).

What this means is that clk is opposite data. This makes a big difference which is unfortunately not documented in timequest at all.

the fact that clock is opposite data means that clock will take some time to arrive at register (clock skew) this skew is negative relative to data and so adds up to tCO at pins

thus the 6.4 ns window has to manage all that delay (clk and data).

In fast devices this may not show up but otherwise it does. The solution is:

1) use fast io register

2) apply pll in compensation mode (if supported) else it gets difficult and I can think of applying multicycle since if data is delayed regularly after one clock you still can sample it correctly provided both min and max actual delays are not hitting the timing window of 2 ns that you have.

you don't really need virtual clock here. moreover your max delay value must be 2 ns. board delay ignored.