Need Help to Verify Timing Constraints On Output Pins to External Device

Rsyc,

Let's assume another simple example where I have such a design: (picture taken from Quartus 2 TimeQuest Timing Anlayzer CookBook pg 1-16 on System Synchronous Output constraints) or even like the picture you have in your TimeQuest user guide pg 16.

https://www.alteraforum.com/forum/attachment.php?attachmentid=10165

The design is just a register that is connected to an output port that is connected to an external device.

in my SDC, should'nt it be just these following steps:

1) create clock for the clock input

2) create virtual clock for the external device

3) and then set otuput delay max and min to 0 ns (simple case)

However I have setup a test module with the above description ( a reg to an output) and constrain the input clock to be 156.25 MHz. Even then, TimeQuest still reports that the design can't meet setup timing.