Need Help to Verify Timing Constraints On Output Pins to External Device

There's a clock inside the FPGA, which I assume is a 6.4ns launch clock, and the external clock that also has a 6.4ns period. (I assume they're edge-aligned). So before we know the delays inside the FPGA, the board_delay or the delay of the external device(tSU), we have a 6.4ns setup relationship to get data across. What the set_output_delay -max does is say how much of that is used externally, which is used up by the tSU of the external device + board delay. So let's say the board_delay is 250ps, and tSU is 2ns, we would do set_output_delay -max 2.25ns and the FPGA now has to get it's data out in less than 6.4-2.25 = 4.15ns. Now if the external delay is 0ns, the external device is chewing up less margin, and hence we're saying the FPGA can get it's data out in up to the whole 6.4ns delay and still meet timing. But the 0ns doesn't mean there's no requirement, just that it's looser. The hold works in a similar manner.