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Altera_Forum
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11 years ago

Need Help to Verify Timing Constraints On Output Pins to External Device

Hi, I'm relatively new in FPGA designing, so forgive me if my question seem simple. The project I am working on involves using a Cyclone V to control 4 external DDS chips (AD9915). So I'...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

If device doesn't manage 6.4 ns for just few registers desugn then it could be that the io register is not used. Just a thought