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Honored Contributor
Honored ContributorNeed Help to Verify Timing Constraints On Output Pins to External Device
Hi, I'm relatively new in FPGA designing, so forgive me if my question seem simple. The project I am working on involves using a Cyclone V to control 4 external DDS chips (AD9915). So I'...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- 0ns external delay doesn't mean no IO requirement, just that the external device isn't chewing up any of the requirement. . --- Quote End --- it is not 0ns external delay. it is 0ns set_output_delay which according to sdc standards is defines as follows: max value = tSU of external device + board delay min value = negative of tH + external delay so if tSU and tH are zero, what does it mean to you? If that isn't the case then why sdc gives such definitions and equations
