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SusanB's avatar
SusanB
Icon for New Contributor rankNew Contributor
6 years ago

Need help to resolve Fatal (vsim-3350) when launching ADC IP simulation (MAX 10) directly from Quartus Prime Lite Edition 18.0.

I have been struggling to get Max 10 ADC IP to simulate out of Quartus.

I have figured out work-arounds to run my own "do" script in modelsim (Altera edition that came with Quartus) but I would like to understand why it is failing to launch using "NativeLink." Here is the full error out of modelsim:

# Loading altera_mf.scfifo(behavior)

# ** Fatal: (vsim-3350) Generic "lpm_width" has not been given a value.

# Time: 0 ps Iteration: 0 Instance: /adc_ip_top_tb/uut/my_adc/modular_adc_0/control_internal/u_control_fsm/ts_avrg_fifo/scfifo_component File: C:/intelFPGA_lite/18.0/modelsim_ase/win32aloem/../altera/vhdl/src/altera_mf/altera_mf.vhd Line: 45146

# FATAL ERROR while loading design

# Error loading design

# Error: Error loading design

# Pausing macro execution

# MACRO ./adc_ip_top_run_msim_rtl_vhdl.do PAUSED at line 25

3 Replies

    • SusanB's avatar
      SusanB
      Icon for New Contributor rankNew Contributor
      6 years ago

      ​Yes, the fatal error vsim-3350 occurs when I try to perform Native link simulation using my own testbench. I don't think this is a result of not waiting long enough, since the modelsim scripts run to the error that I posted. The error occurs in an Altera IP library - altera_mf.scfifo. It is not something that I am using in my design. How do I skip over a fatal error, when modelsim does not allow suppression of fatals? Or how do I fix the fatal, e.g. assign lpm_width to a value, when that is not my code but Altera's? I am looking for a fix for an Altera code bug, not a SusanB code bug (there are plenty of those, but I can fix them myself).

  • Vicky1's avatar
    Vicky1
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    Apologies for the late response,

    Please try to check once with Test Bench Template as follows,

    1. "Processing" -> "Start" -> "Start Test Bench Template Writer"
    2. Check the Test Bench file generated under project directory\simulation\modelsim\ .vt file
    3. Open the .vt file, provide input stimulus & use this module name as test bench name while creating NativeLink
    4. setup the NativeLink & try perform simulation

    Have you made use of mega wizard in your design?

    Could you provide the project file(Project -> Archive Project)?

    Regards,

    Vikas