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Altera_Forum
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10 years ago

Need help for LVDS deserializer

Hello, I need to interface an ADC from Maxim (MAX1437) which have LVDS output (clock, frame, an 12 bits data wide) with a MAX10 FPGA. The goal is to deserialize data's. I develop from Quartus...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Think you can double check on the signal integrity at the output pin also to see if there is any issue.