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Honored Contributor
Honored ContributorNeed help for LVDS deserializer
Hello, I need to interface an ADC from Maxim (MAX1437) which have LVDS output (clock, frame, an 12 bits data wide) with a MAX10 FPGA. The goal is to deserialize data's. I develop from Quartus...
Altera_ForumHonored Contributor
Honored ContributorHi,
I believe you are referring to PLL reference clock of the LVDS instance. The refclk need to be placed to dedicated clock input pin but not normal LVDS IO pin.
