Need help capturing HSync (resolution)

Hi,

I am having big problems trying to capture how many H Sync and how many V Sync occurs during the receive of DVI signal from the PC to my FPGA.

Here is a sample of my code trying to COUNT how many H Sync were received during ONE second:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use ieee.std_logic_unsigned.all;

entity HorizontalCounter is

port(

HSync : IN STD_LOGIC;

pulse : in std_logic;

HCount : out STD_LOGIC_VECTOR( 31 downto 0)

);

end HorizontalCounter;

architecture a of HorizontalCounter is

signal H_Counter : STD_LOGIC_VECTOR( 31 downto 0);

begin

process(HSync,pulse)

begin

if( pulse = '1') then

H_Counter <= (others=>'0');

elsif (HSync'event and HSync = '1' ) then

H_Counter <= H_Counter + 1;

end if;

end process;

HCount <= H_Counter;

end a;

The 'Pulse' here is a signal that is high every one second and then goes to low.

I was expecting the HCount to output how many HSync per second (might be a multiplied by 60) but the out put actually is 4, 8 or 6 depending on the resolution of the PC that feeds the signal in.

I also failed to capture the number of how many VSync per second.

I am trying simply to "Dynamically DETECT" the incoming resolution.

Which also helps me to know when to capture a LINE and process it and when to retransmit it.

Can you please help!

Thanks.