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Honored Contributor
Honored ContributorMy FPGA is not detecting the XOR edge..
I have this verilog code, which depends on either the posedge of the clock or the XOR of my data with its delayed version. assign x1 = data;
assign x2 = ~x1;
assign x3 = ~x2;
assign XORData =...
Altera_ForumHonored Contributor
Honored ContributorMetastability may occur, but actually with a very low likelihood. The present problem is much simpler than metastability, I think.
Because of the undefined timing of input related to clock, the resulting flag has an arbitrary pulswidth starting from zero to a full clock cycle, possibly violating setup and hold times of following logic. If flag is fed to more than one register, each one will see a different version of the signal due to delay differences. One may see a one and another see a zero. If you use flag as input to a state machine, it may even accept an illegal state and never recover without user action (unless you have a safe state machine). Just a short view into the abyss of missing signal synchronisation.
