My FPGA is not detecting the XOR edge..

My suggestion was for synchronous edge detection in general. In reality, as FvM is suggesting, any time you have unrelated clock domains you have to take care of a condition called metastability. Metastability occurs when you sample a data signal while it is transitioning from a 1->0 or 0->1. In this case, you may clock the flip-flop when the input signal has not yet reached a logic 1 or 0. Essentially the flip-flop cannot determine whether it should be a 1 or 0. Now over time it will eventually settle to one or the other. However, it may not occur before the next clock edge.

To take care of this we use a technique called metastability retiming. That's a fancy way of saying just register the input multiple times (like FvM's code). The idea is that even if the first flip-flop is metastable, it's less likely that the second one will be. The more times you register the input signal the lower your probability of having metastability at the final stage. Each FPGA part family actually has different recommendations for how many stages should be used for metastability retiming. I would recommend you use three in your case. And in actuality, There is a setting in Quartus that controls this. Quartus will actually determine where you are doing metastability retiming in your code and adjust the number of stages if you desire.

Jake