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Honored Contributor
Honored ContributorMy FPGA is not detecting the XOR edge..
I have this verilog code, which depends on either the posedge of the clock or the XOR of my data with its delayed version. assign x1 = data;
assign x2 = ~x1;
assign x3 = ~x2;
assign XORData =...
Altera_ForumHonored Contributor
Honored ContributorI confess, that I didn't examine the suggested synchronous edge detector thorougly. It has a nasty design flaw when used with unrelated input signals. The input has to be synchronized to the clock before, otherwise you get occasional errors when the input edge coincides with the clock edge.
// original code
input din;
reg din_r;
wire flag;
assign flag = ^{din,din_r};
always @(posedge clk) din_r <= din;
// modified code, sync input data
input din;
reg din_r;
reg din_sync;
wire flag;
assign flag = ^{din_sync,din_r};
always @(posedge clk)
begin
din_sync <= din;
din_r <= din_sync;
end
