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Altera_Forum
Honored Contributor
Honored ContributorMy FPGA is not detecting the XOR edge..
I have this verilog code, which depends on either the posedge of the clock or the XOR of my data with its delayed version. assign x1 = data;
assign x2 = ~x1;
assign x3 = ~x2;
assign XORData =...
Altera_ForumHonored Contributor
Honored ContributorOkay going with the first suggestion, I sampled my data on each clock and compared my current data level with the previous one to detect the edge.
It worked okay but.. its giving a huge amount of error. to test the design I sent alternating sequence (1010101...) for 100 million bits. I got more than 4% of that wrong!! (i.e i used a counter to count how many bits I am receiving and I am getting 4% less!) eventhough the bits are accurately transmitted as shown on my display. Whenever there is an edge, using the above mentioned method, I increment my bit counter. Whats the problem here? I expected to have some noise but not THAT much! btw, I am transmitting from 1 FPGA to another.
