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Altera_Forum
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17 years ago

My FPGA is not detecting the XOR edge..

I have this verilog code, which depends on either the posedge of the clock or the XOR of my data with its delayed version. assign x1 = data; assign x2 = ~x1; assign x3 = ~x2; assign XORData =...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

As a supplement, I append an asynchronous delay line, basically copied from the stx_cookbook V3.0, used as edge detector. The 10 element line produces a pulse width of about 3 ns according to Quartus timing simulator with Cyclone III. 

module edge_detect (inp,out);
parameter DELAY = 10;
input inp;
output out;
wire  delay_line /* synthesis keep */;
genvar i;
generate
for (i=1; i<DELAY; i=i+1)
  begin : del
    assign delay_line  = delay_line;
  end
endgenerate
assign delay_line  = inp;
assign out = delay_line  ^ inp;
endmodule