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Altera_Forum
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17 years ago

My FPGA is not detecting the XOR edge..

I have this verilog code, which depends on either the posedge of the clock or the XOR of my data with its delayed version. assign x1 = data; assign x2 = ~x1; assign x3 = ~x2; assign XORData =...
Altera_Forum's avatar
Altera_Forum
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17 years ago

The discussed methods of asynchronous edge detection by delay line/XOR may be useful for special cases, where a suitable clock is missing. Apart from the fact, that these design methods aren't supported by usual FPGA compilers (neither Quartus nor any third party tool), they bring a risk of timing violations in the connected logic modules and should be handled with care. So with 40mhz clock for 5mbpsI wouldn't even think of using these techniques. Synchronous edge detection as explained by jakobjones is the means.