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Altera_Forum's avatar
Altera_Forum
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17 years ago

My FPGA is not detecting the XOR edge..

I have this verilog code, which depends on either the posedge of the clock or the XOR of my data with its delayed version. assign x1 = data; assign x2 = ~x1; assign x3 = ~x2; assign XORData =...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

If your data rate is only 5Mbps, then you don't need any inverters whatsoever. Use the approach I described above. Register the data on every clock edge. Then compare the current input data to the last input data. If they are not equal, you have an edge. Use only your clock to adjust the counter. Look at the code I gave in your previous post.

Jake