Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorMy FPGA is not detecting the XOR edge..
I have this verilog code, which depends on either the posedge of the clock or the XOR of my data with its delayed version. assign x1 = data;
assign x2 = ~x1;
assign x3 = ~x2;
assign XORData =...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- A Verilog assign surely causes no delay, it defines an alias signal in logic synthesis. It would require a /* synthesis keep = 1 */ attribute for the wire signals to physically synthesize logic cells. But you most likely need more than two logic cells to build a usable delay line. --- Quote End --- I am using 40MHz clock for 5Mbps data rate. How many gates do u think is enough?
