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Altera_Forum
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17 years ago

My FPGA is not detecting the XOR edge..

I have this verilog code, which depends on either the posedge of the clock or the XOR of my data with its delayed version. assign x1 = data; assign x2 = ~x1; assign x3 = ~x2; assign XORData =...
Altera_Forum's avatar
Altera_Forum
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17 years ago

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Jake

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Yes its for the same issue. Thanx for the reply.

Your first suggestion is OK for me. But about the second one, here is what I understood from your reply:

The synthesis tool is clever enough to know that the inverters I am using r actually dummies, so it actually removes them. So I have to tell the synthesizer to KEEP those gates. Right?

I am working on 5Mbps rate and I am receiving with 40MHz clock. I am keeping the Nyquist rate by having 8 times faster clock.

So how many inverters do u advice me to use, ofcourse with KEEP? How would I make a long enough pulse for my XOR signal?