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Altera_Forum
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17 years ago

My FPGA is not detecting the XOR edge..

I have this verilog code, which depends on either the posedge of the clock or the XOR of my data with its delayed version. assign x1 = data; assign x2 = ~x1; assign x3 = ~x2; assign XORData =...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

--- Quote Start ---

If X2 = NOT data

and X3 = NOT X2

Then X3 = data

it follows that ...

X3 ^ data = data ^ data = 0 for all cases.

There is no XOR edge because you are merely XORing data with itself.

Jake

--- Quote End ---

True. Except that I am XORing my data with its DELAYED version. The above inversion procedures act as a delay. So that finally I XOR my data with delayed version of data. Such XOR will give me a 1 whenever there is an edge transition in my data.

But this is not working on FPGA. Not sure why.

I am working at 40MHz by the way.