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Altera_Forum's avatar
Altera_Forum
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17 years ago

My FPGA is not detecting the XOR edge..

I have this verilog code, which depends on either the posedge of the clock or the XOR of my data with its delayed version. assign x1 = data; assign x2 = ~x1; assign x3 = ~x2; assign XORData =...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

If X2 = NOT data

and X3 = NOT X2

Then X3 = data

it follows that ...

X3 ^ data = data ^ data = 0 for all cases.

There is no XOR edge because you are merely XORing data with itself.

Jake