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Altera_Forum's avatar
Altera_Forum
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8 years ago

My 1st MAX 10 design

Well, I can't hide that I'm a bit scared. This is my 1st FPGA design and I'm doing it without having the MAX 10 here to test first. I know that I might be asking too much :) but do you guys see an...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

As for the other pins, thank you guys very much for pointing that out. I'd have completely missed those.

Here's how it looks now:

https://alteraforum.com/forum/attachment.php?attachmentid=14078&stc=1&d=1503765796"]https://alteraforum.com/forum/attachment.php?attachmentid=14078&stc=1&d=1503765796

CONFIG_SEL is left open as you mentioned. The MAX 10 Pin Connection Guidelines does indeed say:

if you disable the “auto-reconfigure from secondary image when initial image fails” option in the quartus prime software

when generating the pof file, the fpga will always load the configuration image 0 without sampling the physical

config_sel pin during power up.

And the JTAGEN pin is simply pulled up and not connected to pin 8 of the connector, since the JTAG pins are not being used for anything else other than JTAG.

I'm using 1.5k and 12k resistors for the pull ups and pull downs, and not the values suggested by the Altera documentation. I don't see this being critical, and I'm only doing it like this because 1.5k and 12k are the closest resistor values already in use on my board. But is there any possible issues with that?