I am new to the forum, but not VHDL. I am a student at RIT and have taken classes and am very familiar with the language. The questions I have are more of what should my hardware multiplier and divider include? I am designing an 32-bit arithmetic logic unit that can add, subtract, multiply and divide twos compliment signed numbers and one that does unsigned (two separate units). This is part of a larger system that includes a status word. I do know that for an adder/subtractor there is an overflow and carry bit for a status register. What do you need for a multiplier and divider, or better yet, what is typically found? I know there are conditions specified by the IEEE for floating point.

--- Quote Start --- I am new to the forum, but not VHDL. I am a student at RIT and have taken classes and am very familiar with the language. The questions I have are more of what should my hardware multiplier and divider include? I am designing an 32-bit arithmetic logic unit that can add, subtract, multiply and divide twos compliment signed numbers and one that does unsigned (two separate units). This is part of a larger system that includes a status word. I do know that for an adder/subtractor there is an overflow and carry bit for a status register. What do you need for a multiplier and divider, or better yet, what is typically found? I know there are conditions specified by the IEEE for floating point. --- Quote End --- Hi, it is not necessary to develop your own divider or multiplier. Have a look to the Quartus build-in Megawizard. I'm pretty sure you will find most of the things you need. Kind regards GPK

I did look at the megawizard but the divider and multiplier do not have carry, overflow, etc outputs you can specify, only the adder.

building a multiplier is as simple as writing: output <= a * b; a divider has to be pipelined to run at any useful speed, but if you dont mind a slow clock rate, you can write: output <= a / b; I dont know why you are looking for carry on multiplier and divider, they have no meaning.

The alu output is 32 bits. The multiplier, if it is to have no overflow would require 64 bits. The inputs are 32 bits as well. The wizard has no overflow, even if the output is restricted to 32 bits.

Thats no problem. Embedded multipliers allow inputs up to 36 bits, with 72 bit output.

Multiplier and Divider | Altera Community

19 Replies

Altera_Forum
Honored Contributor
14 years ago
What megawizard are you looking at to create a multiplier btw? my one allows inputs up to 256 bits, no overflow problems.

Also, you can just write behavioural VHDL and it will use the correct number of embedded multipliers.

32bit * 32bit doesnt need an overflow.
Altera_Forum
Honored Contributor
14 years ago
The LPM_Mult is what I looked at. If you are multiplying two 32 bit numbers, and the output is restricted to 32 bits, all numbers that have bits above the 32 bit limit will require an overflow detection. For example if you multiply FFFFFFFF * FFFFFFFF, the result will be FFFFFFFE00000001, which exceeds the limit and will not fit on a 32 bit output bus.
Altera_Forum
Honored Contributor
14 years ago
dont use the LPM mult

Use behavioural code.

What FPGA are you targetting?
Altera_Forum
Honored Contributor
14 years ago
Cyclone II
Altera_Forum
Honored Contributor
14 years ago
For me, Quartus 10, The megawizard lets me create an LPM_MULT for a cyclone two that has 2x 256bit inputs and 512 bit output. So no need for any overflow.

Basically, 32 bit multiply is trivial in even the most basic of FPGAs. overflow is never needed.
Altera_Forum
Honored Contributor
14 years ago
And if you understand VHDL, why are you using the megawizard anyway for multiply. What wrong with the * function?
Altera_Forum
Honored Contributor
14 years ago
Yes, I agree that you need no overflow when the output is twice the width of the inputs. That is not the case with me. I do not have a 64 bit output bus, only a 32. Are you misunderstanding something?
Altera_Forum
Honored Contributor
14 years ago
In that case, all you need for a single overflow but is to or the top 32 bits of the output of the multuplier (because you connect the least significant 32 bits of the multiplier to your output) for your unsigned ALU.

for the signed, the output becomes and overflow/underflow. first check is to see if the top 32 bit are all 1 or all 0. If this fails, there is an overflow (in the case of MSB = '1') or underflow (MSB = '0'). Then you compare MSB with bit 31. MSB = '1' and bit31 = '0' means underflow, MSB = '0' and bit31 = '1' mean overflow. You can of course combine all this for a single bit "error".
Altera_Forum
Honored Contributor
14 years ago
How are divide by zero conditions handled in the MegaWizard divider, the LPM_DIVIDER?

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Multiplier and Divider

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