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Altera_Forum
Honored Contributor
Honored Contributormultiplication in fixed_pkg
sir/mam
i am using fixed_pkg_c.vhdl for multiply 0.46 with a wc which is std_logic_vector of 14 bits.i represent 0.46 using sfixed command,but can't understand how to convert std_logic_vector to sfixed or std_ulogic_vector.plzzz help.:cry:6 Replies
Altera_Forumyou need to make the ieee_proposed library.
As you can see, this was the pre-release code. Now its moved to the floatfixlib library, which comes with modelsim. So instead of using ieee_proposed, use floatfixlib instead.- Altera_Forum
thank u sir,
but my question is generally there are one in built librrary called "work". in project there mayy also some vhd program which are designed under this library. then sir, how can i assign library "ieee_proposed" also for those programs.plz make it clear.:cry: - Altera_Forum
you need to add the fixed library library to your project. newer versions of modelsim already have it included.
- Altera_Forum
for information i do the simulation in verilog text fixture.
- Altera_Forum
thank you sir. i have succesfully implement the multiplication. but while simulation,theres occur error.it is shown that library is not assigned.what will i do during simulation? plz suggest:oops:
- Altera_Forum
to convert std_logic_Vector there is a function called
or there is this version:function to_sfixed ( arg : STD_ULOGIC_VECTOR; -- shifted vector constant left_index : INTEGER; constant right_index : INTEGER) return UNRESOLVED_sfixed;
where you can use another signal for sizing information so for example, to convert a 14 bit slv to an sfixed with 6 integer bits and 8 fractional, use the function like this: output <= to_sfixed(my_slv, 5, -8); or you can do this: output <= to_sfixed(my_slv, output);function to_sfixed ( arg : STD_ULOGIC_VECTOR; -- shifted vector size_res : UNRESOLVED_sfixed) -- for size only return UNRESOLVED_sfixed;
