--- Quote Start ---
You're apparently describing the RTL netlist. To see, how it's synthesized, you have to examine the gate level. I also guessed, that a hardware multiplier would be inferred. If you have plenty of them, there's nothing against it, I think. Otherwise you would specify multstyle "logic" for the respective node.
--- Quote End ---
I did go down to the Technology map viewer, they are different, but in the end there is no hardware multiplier used (as witnessed in de Flow Summary). I guess the mapping and fitting are able to deal quite well with the 'one operand' being a fixed value.
--- Quote Start ---
If it was me I will also add a further 16 to the list of addition, so I get rounding up at truncation
--- Quote End ---
We have to make a choice here:
floor (== truncate) : what is in the example code
ceil : should add 31 (and then truncated), or better said add 2^n - 1
financial rounding : like kaz proposes adding 16 or 2^(n-1). This looks interesting ...
Honored Contributor
