Multiplexing bidirectionnal busses

Hi,

I'm working on a project where i need to write some datas directly into ddr via altmemphy controller and to access these datas through Nios.

My problem is that I don't know how to multiplex dq and dqs signals which are bidirectionnal.

I tried to do this as shown in joined picture but i still have an error at compilation :

Error: The bidir pin "ddr_dq[15]" is fed by multiple output buffers

Here is how I wrote the mux :

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY mux IS
PORT(
    mux_select    : in std_logic;
    a_ddr_addr    : in std_logic_vector(12 downto 0);
    a_ddr_ba      : in std_logic_vector(1 downto 0);
    a_ddr_cas_n   : in std_logic;
    a_ddr_cke     : in std_logic;
   
    a_ddr_cs_n    : in std_logic;
    a_ddr_dm      : in std_logic_vector(1 downto 0);
    
    a_ddr_ras_n   : in std_logic;
    a_ddr_we_n    : in std_logic;
    b_ddr_addr    : in std_logic_vector(12 downto 0);
    b_ddr_ba      : in std_logic_vector(1 downto 0);
    b_ddr_cas_n   : in std_logic;
    b_ddr_cke     : in std_logic;
    
    b_ddr_cs_n    : in std_logic;
    b_ddr_dm      : in std_logic_vector(1 downto 0);
   
    b_ddr_ras_n   : in std_logic;
    b_ddr_we_n    : in std_logic;
    
    ddr_addr_out  : out std_logic_vector(12 downto 0);
    ddr_ba_out    : out std_logic_vector(1 downto 0);
    ddr_cas_n_out : out std_logic;
    ddr_cke_out   : out std_logic;
    ddr_clk_n_out : out std_logic;
    ddr_clk_out   : out std_logic;
    ddr_cs_n_out  : out std_logic;
    ddr_dm_out    : out std_logic_vector(1 downto 0);
    ddr_dq_out    : out std_logic_vector(15 downto 0);
    ddr_dqs_out   : out std_logic_vector(1 downto 0);
    ddr_ras_n_out : out std_logic;
    ddr_we_n_out  : out std_logic;
    
    a_ddr_clk_n   : in std_logic;
    a_ddr_clk     : in std_logic;
    b_ddr_clk_n   : in std_logic;
    b_ddr_clk     : in std_logic;
    a_ddr_dq      : in std_logic_vector(15 downto 0);
    a_ddr_dqs     : in std_logic_vector(1 downto 0);
    b_ddr_dq      : in std_logic_vector(15 downto 0);
    b_ddr_dqs     : in std_logic_vector(1 downto 0)
    
    
    );
END ENTITY;
ARCHITECTURE A_mux OF mux IS
BEGIN
ddr_addr_out    <= a_ddr_addr   when (mux_select='1') else b_ddr_addr;
ddr_ba_out      <= a_ddr_ba     when (mux_select='1') else b_ddr_ba;
ddr_cas_n_out   <= a_ddr_cas_n  when (mux_select='1') else b_ddr_cas_n;
ddr_cke_out     <= a_ddr_cke    when (mux_select='1') else b_ddr_cke; 
ddr_clk_n_out   <= a_ddr_clk_n  when (mux_select='1') else b_ddr_clk_n;
ddr_clk_out     <= a_ddr_clk    when (mux_select='1') else b_ddr_clk;  
ddr_cs_n_out    <= a_ddr_cs_n   when (mux_select='1') else b_ddr_cs_n; 
ddr_dm_out      <= a_ddr_dm     when (mux_select='1') else b_ddr_dm;   
ddr_dq_out      <= a_ddr_dq     when (mux_select='1') else b_ddr_dq;   
ddr_dqs_out     <= a_ddr_dqs    when (mux_select='1') else b_ddr_dqs;  
ddr_ras_n_out   <= a_ddr_ras_n  when (mux_select='1') else b_ddr_ras_n;
ddr_we_n_out    <= a_ddr_we_n   when (mux_select='1') else b_ddr_we_n; 
END ARCHITECTURE;

Any idea to solve this problem ?

Thanks

Julien