Honored Contributor
Honored ContributorA long time ago, I worked with async logic. I think you either need to "hold" the present output or drive all outputs to zero for a period long enough for the inputs to resolve then enable the outputs.
If you can find info on TTL (TI's 74xx series) flip-flops were designed to hold the present qout on the leading clock edge then qout could change at the trailing clock edge. Also I think that even tho input t changes, it causes two assigns to change and the race between those 2 are the source of the glitches. Async logic only works if glitches are eliminated and that usually involves generation of a delay to hold while changes resolve or drive to a quiescent state until changes resolve. Async designs usually stress bus transfers and comparing inputs to outputs to determine the duration of the input clock./gate. D FFs are used instead of latches because the double latching prevents propagation of glitches and metastable signals.
