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I just wonder if an Altera 'official' would explain us whether this is also the case for their products.
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As vjAlter explained, Altera FPGAs (and I think, Xilinx and other other vendors as well) have no specific means to support asnychronous designs. There are only a few simple cases, where you can guarantee an unregistered LUT output to be glitch free.
The above quoted statement is however addressing only a part of the problem. It's not sufficient to ask, how a LUT behaves in case of two (or more) simultaneously changing inputs. Due to routing delays, they don't change exactly simultaneously. So only, when all permutations of the changing bits keep the output state, it (hopefully) won't glitch.
As long as you are able to restructure the decoder to achieve this situation, there's a chance to avoid glitches. This has been the case with the binary multiplexer tree from the start of this discussion. It can be build glitch free, but the synthesis tool optimizes the logic in a way, that glitches are created. In this, and only in this case, synthesis attributes can help to enforce a glitch free gate level structure.
The other important hint in vjAlters statement is related to the tools. A synthesis tool, that knows about routing delays would be able to make certain (or possibly all?) asnychronous designs glitch free. But none of the common synthesis tools has this feature, because it's not made to support asynchronous operation.
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