Honored Contributor
Honored ContributorSomething I borrowed from our friends at Xilinx:
this is the original link (http://www.castalk.com/ftopic12373.html) --- Quote Start --- Re: Xilinx LUT behavior question by Peter Alfke » Thu Dec 01, 2005 9:12 am Good question, often asked: No glitch, and that behavior is guaranteed by the decoding structure. Further, if you change two pins, and you know that the output is identical for all 4 permutations of these 2 bits, there also is no glitch. And you can stretch that to 3 pins, where all 8 permutations must give identical results to avoid a glitch, although this last one may be an unrealisticl situation. I have answered this particular question many times over the past 15 years. Peter Alfke, Xilinx Applications --- Quote End --- and --- Quote Start --- Re: Xilinx LUT behavior question by Peter Alfke » Fri Dec 02, 2005 9:15 am Just to get back to the original question (which was kind of academic): my answer still stands. The muxing inside the LUT is done by pass transistors, and the internal capacitance holds the value during non-overlapped switching. So: no glitches. Austin describes glitching in a more general sense, and then mentions on the delay differences of different LUT address inputs. Good info, but does not contradict my statement. Peter Alfke --- Quote End --- I just wonder if an Altera 'official' would explain us whether this is also the case for their products. I'm inclined to think it will be. All the simulations I have done yesterday and today point into that direction.
