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Altera_Forum's avatar
Altera_Forum
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10 years ago

Multiple synchronous clocks and PLL in digital audio application

I am about to make a digital audio transceiver in a Cyclone V device and I am a little bit stuck on the clock strategy (and slightly rusty): On the receiver the data is synchronized on a input ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

It looks my own VHDL is getting rusty.

I suggest this clean way for en1in2 & en1in4 


process(clk)
if rising_edge(clk) then
    en1in2 <= not en1in2;
    en1in4 <= '0';
    if in1in2 = '1' then
        in1in4 <= not en1in4;
    end if;
   
end if;
end process;