Multiple synchronous clocks and PLL in digital audio application

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Given that there are plenty of PLL output counters, you could just use the same PLL to generate 3 clocks, each at the required frequency (256,128 and 64 * fs). Because they all come from the same PLL, the output counters are basically doing what a clock enable would do, producing synchronous clocks at the required frequencies.

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Yes PLL is an option but in my opinion is an overkill remembring issues of lock, simulation, upgrading design, readability ...etc.

you can generate divide by 2 based on inverter:

process(clk)
begin
if rising_edge (clk) then
    en1in2 <= not en1in2;
  
end process;