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Honored Contributor
Honored ContributorMultiple synchronous clocks and PLL in digital audio application
I am about to make a digital audio transceiver in a Cyclone V device and I am a little bit stuck on the clock strategy (and slightly rusty): On the receiver the data is synchronized on a input ...
Altera_ForumHonored Contributor
Honored ContributorGiven that there are plenty of PLL output counters, you could just use the same PLL to generate 3 clocks, each at the required frequency (256,128 and 64 * fs). Because they all come from the same PLL, the output counters are basically doing what a clock enable would do, producing synchronous clocks at the required frequencies.
