Multiple synchronous clocks and PLL in digital audio application

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That is no problem, very slow in comparative sense and you should achieve fmax in cyclone V readily. So I will go for one clock system. generate enable at 1/2 and 1/4 rate and apply clcok to every process together with its enable. Do not gate the clock to divide it.

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Thank you.

Something like this does not gate the clock, right: (Again my HDL is rusty from years of pause)

-- Generate 1/4 rate enable
DIV : process (clk)
begin
  if clk'event and clk='1' then
    enable <= 0 when enable=3 else enable+1;
  end if;
end process;
FSM : process (...)
begin
  if clk'event and clk='1' then
    if enable=0 then      -- Progress the FSM
      next_state <= ...
      ...
    else         -- Keep the current state 
      next_state <= state;
    end if;
  end if;
end process;