Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Multiple synchronous clocks and PLL in digital audio application

I am about to make a digital audio transceiver in a Cyclone V device and I am a little bit stuck on the clock strategy (and slightly rusty): On the receiver the data is synchronized on a input ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

--- Quote Start ---

256*fs is approx 24.5 MHz. fs is 96kHz.

--- Quote End ---

That is no problem, very slow in comparative sense and you should achieve fmax in cyclone V readily. So I will go for one clock system. generate enable at 1/2 and 1/4 rate and apply clcok to every process together with its enable. Do not gate the clock to divide it.