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Altera_Forum
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10 years ago

Multiple synchronous clocks and PLL in digital audio application

I am about to make a digital audio transceiver in a Cyclone V device and I am a little bit stuck on the clock strategy (and slightly rusty): On the receiver the data is synchronized on a input ...
Altera_Forum's avatar
Altera_Forum
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10 years ago

How much is 256*fs?

64*fs, 128*fs, 256*fs are simple doubling. if you run all on 256*fs then all you need is half/quarter enable and you get a clean single clock system.

You can apply multicycles if fmax gets in the way.

alternatively use all three clocks for better power (possibly not worth it) using PLL then all three clocks will be related.