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Honored Contributor
Honored ContributorMultiple constant drivers error?
Hi there,
The problem is that my project is running perfectly on ModelSim but when I've tried to compile it on Quartus 8.1 it gave me multiple constant drivers error. Here is part of the code in verilog:
wire ob_write = (out_buffer_write == 2'b10);
always @(posedge clk)
if(SCK_risingedge)
cs <= ~SSEL;
....
always @(posedge clk ) begin
if (ob_write)
byte_data_sent <= ram_data_out;
end
always @(posedge clk)
out_buffer_write <= {out_buffer_write, (com_read_enable | com_set_enable)};
always @(posedge clk) begin
if (~cs)
byte_data_sent <= 8'h00;
....
4 Replies
Altera_ForumI've read some articles about clock synchronization and domain crossing and solved my problems. Thank you for giving me the direction.
- Altera_Forum
always @(posedge clk ) begin
if (ob_write) byte_data_sent <= ram_data_out; [/INDENT] else if (~cs) byte_data_sent <= 8'h00; [/INDENT] end .... Were you trying to do something like this ? - Altera_Forum
Restating what Kaz said, make assignments to byte_data_sent in only one always block. In the code you showed, you made assignments to byte_data_sent in at least two always blocks.
- Altera_Forum
Hi,
For every signal you must assign within one process only or one comb construct if it is not sequential. Inside the single process you will have multiple assignments for the signal. The compiler decides the logic to drive it then. If then it encounters another drive concurrently then it gets lost...
