New Contributor
New ContributorThank you Sstrell .
Please, can you give me a example shematic or where can i find an example ?
Super ContributorI'm not sure I understand what you're saying. But what I'm saying is to go into the IP Parameter Editor for the PLL and enable additional clock outputs there. So you'd have the c0 like you have in the schematic but also a c1, which can be independently configured.
New ContributorThank you.
Apart from the clk0 leg of the FPGA , my design is in the FPGA .
I try this example, but it does not work .
I did not draw the functions that receive the clocks .
Are there functions "like buffers" in Quartus to multiply the same signals ?
Thanks again in advance .
Regard .
Super ContributorWhy are you adding additional clock dividers on the outputs of the PLL? Just set the output clocks of the PLL to what you want in the parameter settings for the PLL and then connect those outputs to your logic.
When you say "it does not work", what does that mean? What happens? Errors?
New ContributorHello
Thank you for your reply.
Indeed, adding a frequency divider behind a clock signal does not seem normal to me.
Could you tell me how you would go about generating clock signals similar to the last electrical diagram I posted ?
Can we use directly the clock signals generated by the PLL to 50 receiver functions?
Does Quartus take into account the number of receiving functions?
Precisely I do not know if it need buffers?
Example Quartus message : Warning: Can't achieve minimum setup and hold requirement clk33 along 6649 path(s). See Report window for details .
Thank you in advance.
