Multipath timing constraints not giving expected results

Thanks all for your replies.

I have looked further into the issue, and it seems to be because I've been ignoring hold. Adding the extra constraint -hold 1 seems to solve the issue.

I have attached the timing waveforms for the original no multicycle case; the -setup 2 case; and the -setup 2 -hold 1 case.

The waveforms show how when I applied the -setup 2 constraint, but did not re-run synthesis, the 2.47ns hold slack would be reduced to -0.03ns, which I had not noticed before. After running synthesis with the -setup 2 constraint then did not improve the timing due to the hold constraint which I had not considered.

The -setup 2 -hold 1 constraint solves the issue, assuming the -hold 1 constraint is what I want, given the initial schematic. I may end up putting a register, clocked by clk2x, in the middle of the long path. My only concern with this is that I would have to try to place the register in the middle of the path, however Quartus should hopefully move the register along the path as it feels fit in order to offer the best timing.

http://www.alteraforum.com/forum/attachment.php?attachmentid=13233&stc=1 imgur link (the forum seems to remove all the detail from the image) (http://i.imgur.com/pyjaiay.png) http://i.imgur.com/pyjaiay.png