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Altera_Forum's avatar
Altera_Forum
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9 years ago

Multipath timing constraints not giving expected results

Hi all, I am trying to constrain the timing for a design, where a part of the design resembles the included schematic. The paths which are failing timing are between two registers, where the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

How about re-registering both inputs to the mux with clk2x? Then everything before and after the mux is in the clk2x domain and you don't have to worry about the multicycle constraints. You should easily be able to meet the reg-to-reg timing from clk to clk2x without the mux in the path.

Another way to skin the cat if this will work for you.