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Altera_Forum's avatar
Altera_Forum
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9 years ago

Multipath timing constraints not giving expected results

Hi all, I am trying to constrain the timing for a design, where a part of the design resembles the included schematic. The paths which are failing timing are between two registers, where the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

OK, so the signal you have labeled "mux" in the picture, the mux select, is clk2x?

It sounds like you are constraining correctly. It would be helpful to see the waveform tab from a detailed timing report in TimeQuest to make sure your multicycle constraint is correct. You might need a hold multicycle as well since the setup multicycle is moving the hold analysis along with it. Also, are you only failing setup or is hold an issue as well?

It would also be helpful to see the Data Path tab in the report to see where most of the delay is occurring. If it's long IC (interconnect) delay, the registers may be placed too far apart from each other for some reason.