multicycle path

A further note:

It is to do with timing window violation. If a register is clocked at every clk edge (without having enable) then timing has to be correct at every edge.

But if you have registers though clked at every edge but with known enable signal then it becomes possible to exclude from timing those not-enabled clk edges as timing violation there is irrelevant. This translates to treating that register as having 1/2 clk rate or 1/4 depending on multicycle settings.

The problem is how to know which register, that is the job of the tool and designer. Applying the multicycle constraint directly on a regular enable signal is easiest for the tool. Applying it elsewhere(on registers) can lead to chaos and is like playing with fire.

What mystifies me is that why tools can't just do that automatically, after all they see the enable pattern of registers? or don't they?