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Thank you for your answer.
Where state = 2 I assign result and DONE <= '1'.
Where state = 3 you can see DONE <= 'U', but the original code was DONE <= '0': the deassertion was realized there.
In this way, DONE is asserted for one clock cycle. But the result was exactly the same.
The c.i. call hang.
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I guess I misunderstood your notation and problem description. I had understood that when you placed the '***' next to the state=3 deassertion, that when you removed that line you got the hang. I hadn't understood that this line had been there in both broken cases.
Anyway, yes you should look at SignalTap as dsl mentioned and confirm your waveforms match Figure 1-6 of the user guide.
Beyond that, your code is kind of simple so it might be something unrelated. Regarding your mistmatched system ID or timestamp, no it is not normal. It is the tools telling you that you aren't running on the same FPGA design that the software is compiled to expect. For example, maybe your are running on an FPGA that doesn't even have your custom instruction present and hangs for that reason. Furthermore, your 'DONE' bit is being set conditional on the value of 'DATAB', so depending on what your software is supplying, your instruction might take a REALLY long time to execute and simply appear to be hung when it is in fact operating normally.
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