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Altera_Forum
Honored Contributor
10 years ago --- Quote Start --- Which FPGA's DCLK would you use as the source? --- Quote End --- The first FPGA (in mode AS) will generate DCLK for EPCQ and the second FPGA (in mode PS). What broblem for the this DCLK generated by the first FPGA ? DCLK is one and the same for all devises in our scheme. Or in this case phase for our devises will be different into internal scheme of the system clock and data recovery each devises (fpga_1, fpga_2, epcq)? This link on "Arria V Device Handbook Volume 4: Device Basics (November 2011)" https://www.google.ru/url?sa=t&rct=j&q=&esrc=s&source=web&cd=5&ved=0ccgqfjae&url=http%3a%2f%2fcatalog.gaw.ru%2fproject%2fdownload.php%3fid%3d39779&ei=iwclvdtnnybnywpmxocoba&usg=afqjcnhfcya93r_res3gfmrzyt2ji3cxxq&sig2=utk2zlpub15amul6dc_yca&cad=rjt (https://www.google.ru/url?sa=t&rct=j&q=&esrc=s&source=web&cd=5&ved=0ccgqfjae&url=http%3a%2f%2fcatalog.gaw.ru%2fproject%2fdownload.php%3fid%3d39779&ei=iwclvdtnnybnywpmxocoba&usg=afqjcnhfcya93r_res3gfmrzyt2ji3cxxq&sig2=utk2zlpub15amul6dc_yca&cad=rjt) (page 1-61, figure 1-56) illustrate this situation, but for the fpga arria 5. Сan I use this scheme of configuration for the cyclone 5? https://www.alteraforum.com/forum/attachment.php?attachmentid=10485