Forum Discussion
Altera_Forum
Honored Contributor
10 years ago --- Quote Start --- Which FPGA's DCLK would you use as the source? --- Quote End --- The first FPGA generate DCLK for ECPQ and second FPGA which is configured as PS device. What problem for DCLK of first FPGA? For all devises phase equally or not? This link (page 1-60, Figure 1-55) https://www.google.ru/url?sa=t&rct=j&q=&esrc=s&source=web&cd=5&ved=0ccgqfjae&url=http%3a%2f%2fcatalog.gaw.ru%2fproject%2fdownload.php%3fid%3d39779&ei=0tojvbr3esyvsggnl4dwaw&usg=afqjcnhfcya93r_res3gfmrzyt2ji3cxxq&sig2=6kidmjotjhnt73sfepwena&bvm=bv.89947451,d.bgg&cad=rjt is illustrated that situation, but for using the Arria 5. Figure 1-55 http://www.alteraforum.com/forum/attachment.php?attachmentid=10478&stc=1