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Altera_Forum
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8 years ago

multi-core NIOS boot

Hi guys, I'm going to design an FPGA system with two NIOS processors implemented an a Cyclone V device (not the SoC on, the one without ARM core). Each NIOS should be connected to a dedicate...
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Altera_Forum
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8 years ago

I can think of two ways of doing it[list][*]write your own component to generate the reset signal for CPU-B. It would start asserted, and CPU-A would write something to your component to deassert the reset signal. This can be done from CPU-A's application software when it starts, you don't need to modify the bootloader.

[*]instead of keeping CPU-B in reset at startup, put a wait loop very early in its bootloader. It would then wait for a signal from CPU-A before executing the rest. You could use a mailbox component for this purpose, and it could also be used afterwards by your applications if you need some sort of communication between the two CPUs[/list]

application note 458 (https://altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an458.pdf) should give you the information you need about custom bootloaders.