MSGDMA tx descriptor send procedure: (for pc2Fpga transfer data )

Hi experts,

our Arria10 works as a 10GE NIC in x86 Linux PC. we implement "TSE + MSGDMA" to transmit ethernet packet from linux pc to FPGA, MSGDMA will move packet from PC to FPGA, then then the TSE Module will generate ethernet packet out.

But I have a question regarding of “MSGDMA tx descriptor ” issue sequence and conditions :

(1) firstly our linux driver will creates a "tx-descriptor " in msgdma_tx_buffer() , then fill in every elements of " msgdma_extended_desc{..}" (as following) .

csrwr32(lower_32_bits(buffer->dma_addr), priv->tx_dma_desc, msgdma_descroffs(read_addr_lo));
csrwr32(upper_32_bits(buffer->dma_addr), priv->tx_dma_desc, msgdma_descroffs(read_addr_hi));
csrwr32(0, priv->tx_dma_desc, msgdma_descroffs(write_addr_lo));
csrwr32(0, priv->tx_dma_desc, msgdma_descroffs(write_addr_hi));

csrwr32(buffer->len, priv->tx_dma_desc, msgdma_descroffs(len));
csrwr32(0, priv->tx_dma_desc, msgdma_descroffs(burst_seq_num));
csrwr32(MSGDMA_DESC_TX_STRIDE, priv->tx_dma_desc, msgdma_descroffs(stride));
csrwr32(MSGDMA_DESC_CTL_TX_SINGLE, priv->tx_dma_desc, msgdma_descroffs(control));

Once LAST "|GO" Bit is set into msgdma_desc(control), MSGDMA start to transfer data.

【 My question 】: after the first "tx-desc" is issued to FPGA , and MSGDMA now is working on it . Now we have more tx packets coming in soon, thus we need to revoke msgdma_tx_buffer() to start these new packet transferring,

Do we need check any "BUSY" flag of this MSGDMA, or any else in STATUS REGISTER BIT(s) , to decide whether it's safe for usto send the second -> third -> fourth -fifth . .... tx- desc to FPGA ?

Do we need wait for CSR “STATUS REGISTER # BIT0 (BUSY flag) ” to be zero, then start the next "tx_desc", Or we dont need care that ?

Thanks a lot