Honored Contributor
Honored ContributorHi Steve,
Let me come in here with some background on the motor control toolflow using DSP Builder Advanced blockset highlighted in the whitepaper... What Altera are showcasing here is a Matlab / Simulink design flow where a non-HDL designer can design their algorithm in Simulink with DSP Builder and then have the tool automatically generate VHDL for you that is optimized for the required latency, resource usage & device family. Folding or TDM is supported to allow hardware re-use of blocks such as multipliers and adders, and floating or fixed point data types can be mixed as necessary. There are two demos shipped with DSP builder that cover a floating and fixed-point implementation of an example FOC algorithm with speed and position control. As James mentions, another approach is to develop your own custom VHDL for the functions (park, clark, cordic, PI control etc) and create a bespoke implementation with good results. However this flow requires expert VHDL knowledge to get good implementation results whereas the DSP builder flow lets you design the algorithm and generate the VHDL automatically. So here we are trading off hand-written VHDL for a tool flow that generates the VHDL for you - with hopefully close to the same performance. We have shown the DSP builder implementation of the FOC working reliably in hardware on the FalconEye FPGA dev kit from EBV. This uses a sample rate of 16kHz. The FalconEye reference design is available from EBV and the DSP builder FOC implementation is available from Altera. Both designs require license agreements (free of charge) to be signed for access to them. -Kevin
