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Altera_Forum
Honored Contributor
13 years agoTime Division Multiplexing? Hmmm. I don't see the need for this. Typically, a current loop FOC needs around 2500 LE's for a 12 bit datapath, that includes the clark transform, vector rotators, PI controllers, and SVPWM. I am not sure what Altera is touting here, but an FOC with a speed loop, sequential control unit to handle inputs, etc. shouldn't be any more that 4500 LE's. Of course, I implemented the rotators with a CORDIC algorithm, as well as compute square root with the vectoring mode of the CORDIC, so that helps. But I ran my latest FOC design at 100 MHz base clock for the entire design, with a loop execution time of around 1 usec.
Best, James