Forum Discussion
Altera_Forum
Honored Contributor
13 years agoHi James
Thanks for your input. May I ask if your implementation is done in floating point or fixed point? Also one of the selling point in the DSP builder is the logic Folding (Time-devision Multiplexing) that can minimize resource usage. In our situation, the FPGA is limited to Cyclone III 3C25 or 3C40, the LEs may be a limiting factor. Does the Aldec tool you mentioned do the same thing (TDM or somthing similar, Currently I am only using the ModelSim from Altera). Your input is greatly appreciated. Many thanks in advance Steve Chan